The present invention relates generally to signal processors, and more particularly, to techniques that measure latency of a digital processor or circuit.
A digital signal processor or circuit can have a well defined latency. For simple processors the latency is just a count of the number of clocks of delay for the signal as it passes through the circuit. More complex processing can change the sample rate or delay the signal by an amount that is not equal to a sample interval.
More particularly, a digital signal processor delays the signal as the signal is processed. The delay of some processors such as a shift register, for example, is a count of the number of clocks required to shift the signal through the shift register. A filter will delay the signal by an amount depending on the filter coefficients. The delay may be a fixed number of samples, but an interpolator will change the sample rate, introducing a complication into the calculation of delay. Even a simple filter with no change in the sample rate may have a delay that is not an integer number of samples. Finite Impulse Response (FIR) filters with an even number of taps that are symmetrical about the center will have a delay that is equal to half the number of samples in the filter plus one half sample.
More complex processing will change the sample rate while correcting for differences in the input and output sample rates. Examples of such processors are those that correct a plesiochronous input sample rate to the station clock standard in a processor that is connected to an outside source with a different clock.
Another complication is the measurement of the latency when the processing changes the frequency of the signal. When the processing includes conversion to an analog form, the latency becomes harder to measure. There is no well defined output clock to provide a sample time that can be used as a reference.
A typical measurement of latency in the past introduces a pulse at the input to the processor and measures the time required for the pulse to propagate through the processor to the output. A simple time-interval measurement from the rising edge of the input pulse to the rising edge of the output pulse will measure the latency of the processor.
An alternative technique that is useful in limited circumstances is that used by a network analyzer. The network analyzer measures the change in phase from the input to the output. The delay through a simple circuit is the group delay through the circuit. The network analyzer measures the change of phase at a sequence of different frequencies then calculates the group delay as the rate of change of phase. This technique works well when the input sample rate is the same as the output sample rate so that the input phase can be compared with the output phase easily.
When the processor changes the sample rate or performs resampling to correct for an asynchronous input, these techniques will not be able to measure latency. The latency will not be an integer number of samples of the input sample rate, so a pulse at the input may be delayed by an amount that results in an output pulse that is between output samples.
The processing may destroy the pulse as happens when the frequency of the sample is shifted. Changing the sample rate of a complex signal, a signal with an in-phase and quadrature component, typically changes the center frequency of the signal as well. That is, a signal centered at one fourth the input sample will end at a frequency centered at one fourth the output sample rate. This processing keeps the bandpass signal centered in the available output bandwidth, but shifts the frequency in the processing. When the pulse is ill defined at either the input or the output, the measurement of the time between the input pulse and the output pulse is not possible.
It is an objective of the present invention to provide for improved techniques that measure latency of a digital processor or circuit.